Multigigabit LDPC decoders are demanded by standards like IEEE 802.15.3c and IEEE 802.11ad. To achieve the high throughput\r\nwhile supporting the needed flexibility, sophisticated architectures are mandatory. This paper comprehensively presents the design\r\nspace for flexible multigigabit LDPC applications for the first time. The influence of various design parameters on the hardware\r\nis investigated in depth. Two new decoder architectures in a 65 nm CMOS technology are presented to further explore the design\r\nspace. In the past, the memory domination was the bottleneck for throughputs of up to 1 Gbit/s. Our systematic investigation of\r\ncolumn- versus row-based partially parallel decoders shows that this is no more a bottleneck for multigigabit architectures. The\r\nevolutionary progress in flexible multigigabit LDPC decoder design is highlighted in an extensive comparison of state-of-the-art\r\ndecoders.
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